1. Field of the Invention
The present invention relates to wafer structures and a method of making the same. More particularly, the invention relates to a wafer structure containing an insulation layer.
2. Description of Related Art
Wafer structures having a "buried insulation" layer are particularly useful for semiconductor devices made via a BiCMOS process. The BiCMOS process is an integrated circuit processing technology which allows bipolar transistors to be formed within substrate wells containing complementary metal-oxide semiconductor (CMOS) transistors. An example of a BiCMOS semiconductor device is one in which "power-hungry" emitter coupled logic (ECL) bipolar circuits are used on a silicon-on-insulator (SOI) structure. The ECL circuits act as logic elements and bipolar drivers. One disadvantage of these ECL circuits is that they produce sufficient heat that the generated heat becomes trapped and gives rise to temperatures unacceptable for normal device operation.
In addition to temperature sensitivity, silicon devices are sensitive to radiation (e.g., .alpha.-radiation and cosmic radiation). In order to decrease the radiation sensitivity of the silicon device, the collection volume of the device has to be reduced for hole/electron pairs generated by the radiation impact along the radiation path. The collection volume can be reduced by incorporating a "buried insulation" layer in the silicon device structure.
Recently, the technology for forming "buried insulation" layers has advanced to the stage of manufacturing quantities. In particular, thermally grown SiO.sub.2 is used as the buried insulation layer. Bonding two oxide grown wafers can be achieved at an elevated temperature (900.degree. to 1100.degree. C.) whereby the two oxide layers become a single oxide layer. The excess silicon on the device wafer is then removed, first by grinding, then by lapping, and finally by chem.-mech. polishing. On the commercial market, 2 .mu.m thick silicon above a buried 5000 .ANG. thick SiO.sub.2 oxide layer is obtainable, for example, from Shin-Etsu Handotai (S.E.H.) of Tokyo, Japan.
A buried isolation layer of thick thermal SiO.sub.2 oxide (5000 .ANG.) can also be used for reducing heat build-up of the ECL circuits on an SOI structure, if a heat conducting path is provided. The use of thermally grown SiO.sub.2, by itself, has disadvantages. For instance, the thermal resistance of the oxide is a function of thickness. The thermal resistance of the oxide layer can be minimized by making the layer thin, however, this would result in undesired increased capacitance effects. In addition, the thermal expansion coefficient of SiO.sub.2 (5.times.10.sup.-7 C.sup.-1) is not well matched with the thermal expansion coefficient of silicon (32.times.10.sup.-7 C.sup.-1).
An alternative method for keeping a device cool is to incorporate a polycrystalline diamond layer within the semiconductor device structure as shown in U.S. Pat. No. 4,981,818 entitled "Polycrystalline CVD Diamond Substrate For Single Crystal Epitaxial Growth Of Semiconductors" and granted Jan. 1, 1991 to Anthony et al.. In the '818 patent, a chemical vapor deposited (CVD) diamond layer is formed on a single crystal of silicon. During the deposition of the diamond layer, an intermediate layer of single crystal SiC forms between the single crystal of silicon and the polycrystalline CVD diamond layer. The silicon is then completely removed, via etching, to reveal the SiC layer supported on the polycrystalline CVD diamond layer. A semiconductor layer is thereafter epitaxially grown on the exposed single crystal of SiC. A single crystal semiconductor polycrystalline CVD diamond mounted device structure is thus produced.
A device produced via the teaching of the '818 patent, however, has disadvantages. For instance, the crystal quality of the semiconductor grown epitaxially on the SiC is subject to defects, such as, lattice mismatch. In addition, the CVD diamond layer becomes the support substrate for the semiconductor device, thus, necessitating a relatively thick CVD diamond layer. Furthermore, since the diamond substrate of the '818 patent is exposed, any subsequent device fabrication steps of high temperature, high energy processes in oxygen (such as oxidation, plasma ashing, etc.) will attack the substrate. Therefore, it is very difficult to perform process steps with the '818 diamond substrate for processes, such as, isolation trench formation, field isolation, and resist stripping.
It would thus be desirable to provide a wafer structure having a buried insulation layer which is free of the above identified problems. Such a structure should also provide a substrate which is substantially free of lattice mismatch defects and further provide optimal thermal dissipation. Still further, such a structure should be suitable for isolation trench formation.